The continued increase in density of integrated circuits and correlative demand for circuit devices that consume less power has forced the semiconductor industry to consider new manufacturing techniques that enable fabrication of devices on a submicron scale. These trends also have made dynamic random-access memory arrays ("DRAMs") an attractive option for many applications.
In the fabrication of DRAMs, it is essential that the plates of the storage capacitor have sufficient surface area to retain an adequate charge, despite the presence of parasitic effects that permit charge to leak from the plates during circuit operation. Maintenance of adequate storage capacitance is particularly challenging because future generations of DRAMs will require substantially higher device densities.
It is known that storage capacitance can be enhanced without increasing the storage electrode height or the area that the storage capacitor occupies in the cell by using HSG to form the storage node electrode. Electrodes formed with HSG have greater surface area and, therefore, greater capacitance for a given footprint area because HSG has a rough granular surface. Currently known methods for forming HSG include (1) depositing HSG directly on a wafer utilizing a conventional technique, e.g. low pressure chemical vapor deposition; (2) depositing a starting material, e.g. amorphous silicon ("a-Si"), on a wafer and then annealing the starting material layer to form HSG; and (3) depositing a starting material on a wafer, seeding the starting material with a species and then annealing the seeded layer at the same temperature at which seeding took place to form HSG. See U.S. Pat. No. 5,407,534 (U.S. Class 156/662), issued Apr. 18, 1995, to Thakur et. al., and the references cited therein for a further discussion of currently known methods.
These methods, however, are plagued by several drawbacks, including the following: (1) roughness of the HSG is suboptimal, resulting in lower capacitances; (2) starting material is converted into HSG over a very narrow temperature range, requiring precise process temperature controls; (3) process flows are inflexible; (4) both seeding and annealing are performed at substantially identical temperatures in the same process flow so that seeding and annealing conditions are not varied and, therefore, not optimized independently of each other; (5) only silicon hydrides, e.g., disilane (Si.sub.2 H.sub.6), are used as seeding materials; (7) disilane seeding materials always are used in diluted form, resulting in slower seeding; (8) seeding is time consuming; and (9) seeding is sparse, resulting in smoother HSG. It can be appreciated that many of these drawbacks are interrelated.